Drive circuit for switching power supply

ABSTRACT

A drive circuit for a switching power supply includes a driving element (11, 12) for generating a drive signal (SD), and a transformer (15) for outputting the drive signal input via a capacitive element to a primary winding (15a) thereof (14), to a main switching element (21) from a secondary winding (15b) thereof. The drive circuit (3) is constructed such that breakage of the main switching element (21) can be prevented while permitting an increase in the range of switching control. The drive circuit (3) is characterized by comprising an inductive element (16) having an inductance value smaller than at least a value of an excitation inductance of the primary winding (15a) and allowing series resonance to be produced between the capacitive element (14) and the inductive element (16).

TECHNICAL FIELD

This invention relates to a drive circuit for a switching power supply,and more particularly to a drive circuit for a switching power supply,for delivering a drive signal to a main switching element via a drivetransformer.

BACKGROUND ART

Conventionally, a power supply unit 41 shown in FIG. 6 is well known asa switching power supply unit including a drive circuit of theabove-mentioned kind. The power supply unit 41 is comprised of a controlcircuit 2 for generating a switching signal SS, a drive circuit 42 forcarrying out power amplification of the switching signal SS, and a maincircuit 4 for generating a DC voltage Vo by performing switchingoperation in synchronism with a drive signal SD delivered from the drivecircuit 42.

The drive circuit 42 is comprised of a pair of an npn transistor 11 anda pnp transistor 12 forming a complementary circuit, a pull-up resistor13, a capacitor 14 for blocking DC current, and a drive transformer 15having a primary winding 15 a and a secondary winding 15 b at a turnsratio of 1:1. Further, the main circuit 4 is comprised of an n-channelMOS FET 21 serving as a main switching element, bias resistors 22 and23, a switching transformer 24, and a rectifying and smoothing circuit25.

In the power supply unit 41, the control circuit 2 receives a feedbacksignal SF delivered from the main circuit 4, and outputs a switchingsignal SS having a pulse width (or frequency) dependent on the feedbacksignal SF. Then, the transistors 11 and 12 operate alternately insynchronism with the switching signal SS delivered from the controlcircuit 2, to carry out the power amplification of the switching signalSS for generation of the drive signal SD, and delivers the generateddrive signal SD to the primary winding 15 a of the transformer 15 viathe capacitor 14. As a result, the drive signal SD is induced in thesecondary winding 15 b of the transformer 15 and supplied to the FET 21.In this case, if the duty ratio of the switching signal SS is 50%, theFET 21 has a voltage VGS of VCC/2 between its gate and source during theON time period TON of the switching signal SS, as shown in FIG. 5, and avoltage VGS of −VCC/2 during an OFF time period TOFF of the same. As aresult, during the ON time period TON over which the voltage VGS isabove a threshold voltage Vth, the FET 21 is controlled to an ON stateto output a drain current ID shown in the figure to the primary winding24 a of the transformer 24. Then, the rectifying and smoothing circuit25 rectifies and smoothes a voltage induced in the secondary winding 24b of the transformer 24, to thereby generate a DC voltage Vo.

DISCLOSURE OF INVENTION

From a study of the above prior art, the inventor found out thefollowing problems. In the conventional power supply unit 41, if theduty ratio of the switching signal SS is e.g. 50%, the FET 21 has thevoltage of ±VCC/2 applied between the gate and source thereof duringoperation of the control circuit 2. Accordingly, since the transformerhas the turns ratio of 1:1, the voltage of VCC/2 is constantly appliedbetween opposite ends of the capacitor 14. This means that the capacitor14 constantly stores energy. For this reason, when the control circuit 2stops operating, the stored energy is released from the capacitor 14,whereby a series resonance phenomenon dependent on a capacitance of thecapacitor 14 and an excitation inductance of the primary winding 15 a ofthe transformer 15 occurs in a closed circuit formed by the capacitor14, the primary winding 15 a, and the emitter and collector of thetransistor 12. In this case, if the capacitance of the capacitor 14 isrepresented by a value C and the excitation inductance of the primarywinding 15 a by a value L, a series resonance frequency f in the seriesresonance phenomenon is expressed by the following formula (1):

f=1/(2·π·(L·C)^(0.5))  (1)

Therefore, during production of the series resonance, a series resonancevoltage having a voltage waveform W11 is induced in the secondarywinding 15 b of the transformer 15, and the voltage waveform W11 isapplied between the gate and source of the FET 21. In this case, sincethe excitation inductance of the primary winding 15 a is large, theseries resonance frequency f provides a period which is extremely longerthan a period (TS) of the switching signal SS. For this reason, duringtime periods between times t11 and t12 and between times t13 and t14,over each of which the voltage waveform W11 is above the thresholdvoltage Vth, an excessively large amount of drain current ID flows tothe FET 21 as shown by respective current waveforms W12 and W13. As aresult, magnetic saturation occurs in the transformer 24, which, forinstance, causes a further excessively large amount of drain current IDto flow, setting up a vicious circle. Thus, the conventional powersupply unit 41 suffers from a problem that the FET 21 and thetransformer 24 can be broken due to the series resonance phenomenonwhich occurs when the control circuit 2 stops operating. To avoid thisvicious circle, the conventional power supply unit 41 controls the dutyratio of the switching signal SS within a range below 50% to reduce theenergy stored in the capacitor 14 to thereby reduce resonance energyduring production of the series resonance. For this reason, theconventional power supply unit 41 is not allowed to control the dutyratio of the switching signal SS to 50% or more, and hence the range ofswitching control is narrow.

The invention has been made to solve the above problems, and it is amain object of the invention to provide a drive circuit for a switchingpower supply, which is capable of preventing breakage of a mainswitching element and at the same time permits an increase in the rangeof switching control.

The drive circuit for a switching power supply includes a drivingelement for generating a drive signal for driving a main switchingelement, and a transformer for delivering the drive signal input via acapacitive element to a primary winding thereof, to the main switchingelement from a secondary winding thereof, the drive circuit beingcharacterized by comprising an inductive element having an inductancevalue smaller than at least a value of an excitation inductance of theprimary winding and allowing series resonance to be produced between thecapacitive element and the inductive element.

This drive circuit increases the resonance frequency in the resonancephenomenon caused by the capacitive element and the inductive elementupon stoppage of operation for generating power. Therefore, since theperiod of the series resonance frequency is shortened, a time periodover which the resonance voltage waveform is above a threshold voltageof the switching element becomes shorter. For this reason, the switchingelement becomes difficult to turn on, and even when the switchingelement is turned on, the maximum value of a current flowing is reduced,whereby magnetic saturation of the switching transformer connected tothe main switching element is prevented and hence breakage of the mainswitching element and the switching transformer is prevented. Further,by setting a capacitance value of the capacitive element to a suitablevalue, it is possible to minimize the amount of energy stored in thecapacitive element. In this case, series resonance energy itself isreduced, which ensures prevention of the magnetic saturation of theswitching transformer. As a result, the duty ratio of the drive signalcan be increased, whereby it is also possible to increase the range ofswitching control.

Preferably, the capacitive element and the inductive element haverespective element constants that determine a resonance frequencyexceeding one fifth of a frequency of the drive signal. By thisconstruction, the ON time period of the switching element is furthershortened. In this case, since the magnetic saturation of the switchingtransformer is reliably prevented, it is possible to ensure preventionof the breakage of the main switching element and the switchingtransformer.

Further preferably, the capacitive element and the inductive elementhave respective element constants that cause the resonance frequency toexceed the frequency of the drive signal. By this construction, the ONtime period of the switching element is further shortened, and hence themagnetic saturation of the switching transformer is reliably prevented,whereby it is possible to more positively prevent the breakage of themain switching element and the switching transformer.

Further, the inductive element can be connected in parallel with theprimary winding. Furthermore, a series circuit formed by the inductiveelement and a damper resistor can be connected in parallel with theprimary winding. In the case of the series circuit being connected inparallel with the primary winding, energy generated during the seriesresonance phenomenon caused by the capacitive element and the inductiveelement is lost at the damper resistor. Therefore, the resonancephenomenon is quickly controlled, which makes it possible to morepositively prevent the breakage of the main switching element and theswitching transformer.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram of a power supply unit 1 according to afirst embodiment of the invention;

FIG. 2 is a diagram which is useful in explaining operation of the powersupply unit 1 according to the first embodiment and shows a voltagewaveform of a voltage VGS between the gate and source of an FET 21 aswell as a current waveform of a drain current ID flowing through the FET21;

FIG. 3 is a circuit diagram of a power supply unit 31 according to asecond embodiment of the invention;

FIG. 4 is a diagram which is useful in explaining operation of the powersupply unit 31 according to the second embodiment and shows a voltagewaveform of a voltage VGS between the gate and source of an FET 21 aswell as a current waveform of a drain current ID flowing through the FET21;

FIG. 5 is a diagram which is useful in explaining operation of aconventional power supply unit 41 and shows a voltage waveform of avoltage VGS between the gate and source of an FET 21 as well as acurrent waveform of a drain current ID flowing through the FET 21; and

FIG. 6 is a circuit diagram of the conventional power supply unit 41.

BEST MODE OF CARRYING OUT THE INVENTION

The invention will now be described in detail with reference to thedrawings showing preferred embodiments thereof. In these embodiment, adrive circuit for a switching power supply, according to the invention,is applied to a switching power supply unit.

(First Embodiment)

Referring first to FIG. 1, there is shown the circuitry of a powersupply unit 1. The power supply unit 1 includes a control circuit 2 forgenerating a switching signal SS, a drive circuit 3, and a main circuit4. The drive circuit 3 is comprised of a pair of an npn transistor 11and a pnp transistor 12, which forms a complementary circuit, a pull-upresistor 13, a capacitor 14 corresponding to a capacitive element of theinvention for blocking a DC current, a drive transformer 15 having aprimary winding 15 a and a secondary winding 15 b at a turns ratio of1:1, and an inductor 16 connected in parallel with the primary winding15 a and corresponding to an inductive element of the invention. Themain circuit 4 is comprised of an n-channel MOS FET 21, which is a mainswitching element, bias resistors 22 and 23, a switching transformer 24,and a rectifying and smoothing circuit 25.

In the embodiment, a capacitance value C of the capacitor 14 and aninductance value L16 of the inductor 16 in the drive circuit 3 aredefined such that they satisfy the following conditions. That is, first,the capacitance value C of the capacitor 14 is defined within a rangeshown by the following formula (2) such that the amount of stored energyis minimized when the control circuit 2 stops operating and at the sametime, a voltage VGS which is sufficiently higher than a thresholdvoltage Vth can be supplied between the gate and source of the FET 21,which corresponds to the main switching element of the invention:

20·Ciss≦C≦100·Ciss  (2)

where Ciss represents an input capacitance of the FET 21.

Further, after the capacitance value C of the capacitor 14 is set to apredetermined value within the range described above, the inductancevalue L16 is defined according to the following formula (3) such that anON time period TON of the FET 21 energized due to series resonancebecomes equal to or shorter than 50% of a period TS of the switchingsignal SS. The inductance value L16 defined according to the formula (3)assumes a value which is sufficiently smaller than an excitationinductance value L of the primary winding 15 a. More specifically, ifthe excitation inductance value L of the primary winding 15 a is 1 mH,for instance, the inductance value L16 of the inductor 16 is equal toapproximately 10 μH. In the formula (3), the value fSW represents afrequency of the switching signal SS.

2·π·(L 16·C)^(0.5)≦1/fSW  (3)

However, it was demonstrated by the inventor's experiment that it ispossible to prevent overcurrent from braking the FET 21 and thetransformer 24, by setting the inductance value L16 within a rangedefined by the following formula (4). In the following, an example ofthe inductance value L16 defined according to the formula (4) will bedescribed.

2·π·(L 16·C)^(0.5)≦5/fSW  (4)

Next, the rationale of the above formula (4) will be described. Theformula (4) means that it is required to set a resonance period of theseries resonance caused by the inductor 16 and the capacitor 14 suchthat it is equal to or shorter than a time period which is five times aslong as the period TS of the switching signal SS. On the other hand, amagnetic flux density of the transformer 15 is increased with anincrease of the ON time period (i.e. the period TS) of the switchingsignal SS. Further, although a saturation magnetic flux density of aferrite core used in the transformer 15 is generally equal to 5000 gaussat the maximum, in the power supply unit in actual use, the magneticflux density actually operating during normal switching operationperformed in response to the switching signal SS is defined to be heldat a value which is equal to or smaller than 1000 gauss. For thisreason, by setting the resonance period of the series resonance suchthat it is equal to or shorter than the time period which is five timesas long as the period TS of the switching signal SS, it is possible tocontrol the magnetic flux density of the transformer 15 duringproduction of the series resonance within the maximum value of fivetimes larger than the operating magnetic flux density. Therefore, evenduring occurrence of the series resonance phenomenon, the transformercan be operated with its magnetic flux density held at a level equal toor below 5000 gauss, which ensures prevention of magnetic saturation.The above is the rationale of the formula (4).

Next, description will be made of the operation of the power supply unit1, particularly when the control circuit 2 stops operating, withreference to FIG. 2.

When the switching signal SS having a pulse width (or frequency)dependent on the feedback signal SF output from the main circuit 4 isdelivered from the control circuit 2, the transistors 11 and 12 operatealternately in synchronism with the switching signal SS to carry outpower amplification of the switching signal SS to thereby generate thedrive signal SD. The drive signal SD is output to the primary winding 15a of the transformer 15 via the capacitor 14 and thereby induced in thesecondary winding 15 b. Then, the induced drive signal SD is supplied tothe gate of the FET 21. In this case, as shown in FIG. 2, if the dutyratio of the switching signal SS is 50%, for instance, the FET 21 has avoltage VGS of VCC/2 between its gate and source during the ON timeperiod TON of the switching signal SS, and a voltage VGS of −VCC/2during the OFF time period TOFF of the same. As a result, during the ONtime period TON over which the voltage VGS is above the thresholdvoltage Vth, the FET 21 is controlled to the ON state, to output a draincurrent ID shown in the figure to the primary winding 24 a of thetransformer 24. Then, the rectifying and smoothing circuit 25 rectifiesand smoothes the voltage induced in the secondary winding 24 b of thetransformer 24, to thereby generate a DC voltage Vo.

On the other hand, when the control circuit 2 stops operating, theseries resonance phenomenon occurs in the closed circuit formed by thecapacitor 14, the parallel circuit formed by the primary winding 15 aand the inductor 16, and the emitter and collector of the transistor 12.In this case, since the excitation inductance value L of the primarywinding 15 a is sufficiently small and negligible compared with theinductance value L16 of the inductor 16, the series resonance frequencyis determined based on the capacitance of the capacitor 14 and theinductance value L16 of the inductor 16. The series resonance frequencyf1 is expressed by the following formula (5):

f 1=1/(2·π·(L 16·C)^(0.5))  (5)

During production of the series resonance, a series resonance voltagehaving a voltage waveform W1 shown in FIG. 2 is induced in the secondarywinding 15 b of the transformer 15, and the voltage waveform W1 isapplied between the gate and source of the FET 21. In this case, theperiod of the series resonance frequency f1 is within a range of one tofive times as long as the period TS of the switching signal SS, so thattime periods between times t1 and t2 and between times t3 and t4, overeach of which the voltage waveform W1 is above the threshold voltageVth, are each sufficiently shorter than the time periods between thetimes t11 and t12 and between the times t13 and t14 during the seriesresonance in the conventional power supply unit 41. Therefore, as shownby waveforms W2 and W3 in the figure, the maximum value of the draincurrent ID flowing through the FET 21 during the time periods betweenthe times t1 and t2 and between the times t3 and t4 becomes slightlylarger than that of the drain current ID in normal switching operation,whereby excessive conduction of the drain current ID is prevented.

As described above, according to the power supply unit 1, since theperiod of the series resonance produced when the control circuit 2 stopsoperating can be controlled within a time period five times longer thanthe period of the switching signal SS (preferably, it is shorter thanthe period of the switching signal SS), it is also possible to preventexcessive conduction of the drain current ID. As a result, the magneticsaturation of the transformer 24 can be prevented reliably, whereby itis possible to prevent breakage of the FET 21 and the transformer 24caused by the series resonance phenomenon. It should be noted that ifthe period of the series resonance frequency f1 is controlled to ashorter period than the period TS of the switching signal SS, the timeperiod over which the resonance voltage waveform is above the thresholdvoltage vth can be shortened. As a result, the FET 21 becomes difficultto turn on, and even when it is turned on, the maximum value of thedrain current ID flowing through the FET 21 becomes smaller. Therefore,it is possible to prevent the magnetic saturation of the transformer 24and the breakage of the FET 21 and the transformer 24 caused by theseries resonance phenomenon more reliably.

Further, by setting the capacitance value C of the capacitor 14 to asuitable value to minimize the amount of stored energy of the capacitor14 when the control circuit 2 stops operating, it is possible to reducethe series resonance energy itself, whereby the breakage of the FET 21and the transformer 24 are positively prevented. Thus, differently fromthe conventional power supply unit 41, the duty ratio of the switchingsignal SS can be controlled to 50% or more, so that the range ofswitching control can be increased.

(Second Embodiment)

Next, description will be made of circuitry and operation of the powersupply unit 31 which is formed by modifying part of the power supplyunit 1, with reference to FIG. 3. Components corresponding to those ofthe first embodiment are indicated by identical reference numerals, anddetailed description thereof will be omitted.

As shown in the figure, the power supply unit 31 is distinguished fromthe power supply unit 1 in that it has a drive circuit 5 in which aseries circuit formed by an inductor 16 and a damper resistor 17 isconnected in parallel with a primary winding 15 a of the transformer 15.

When a control circuit 2 stops operating, a series resonance phenomenonoccurs in a closed circuit formed by a capacitor 14, a parallel circuitformed by the series circuit of the inductor 16 and the resistor 17 andthe primary winding 15 a, and the emitter and collector of a transistor12. In this case, energy stored in the capacitor 14 is lost at theresistor 17 during production of series resonance. For this reason, asshown in FIG. 4, a voltage waveform W4 of a voltage VGS applied betweenthe gate and source of an FET 21 during production of the seriesresonance has a characteristic of being attenuated more rapidly than thevoltage waveform W1 in the case of the power supply unit 1, though theperiod is identical between the two waveforms. Accordingly, the voltagewaveform W4 does not exceed a threshold value Vth except during a timeperiod between times t5 and t6, which is even shorter than the timeperiod between the times t1 and t2, i.e. the time period duringproduction of series resonance in the unit 1. Therefore, the FET 21becomes difficult to turn on between the times t5 and t6, and as shownby a waveforms W5 in the figure, the maximum value of a drain current IDflowing through the FET 21 during the time period becomes substantiallyequal to or slightly smaller than that of the drain current ID in normalswitching operation. As a result, excessive conduction of the draincurrent ID is prevented reliably.

As described above, according to the power supply unit 31, since theseries circuit formed by the inductor 16 and the resistor 17 isconnected in parallel with the primary winding 15 a, it is possible tocontrol the resonance phenomenon quickly and hence further reduce thedrain current ID flowing through the FET 21 during production of theseries resonance. This more reliably prevents magnetic saturation of thetransformer 24, which ensures more positive prevention of breakage ofthe FET 21 and the transformer 24 caused by the series resonancephenomenon.

It should be noted that the present invention is not limited to theabove embodiments, but the construction thereof can be modified asrequired. For instance, although in each of the power supply units 1 and31 according to the embodiments of the invention, the FET is used as themain switching element of the invention, this is not limitative, but itis possible to employ various kinds of switching elements such astransistors. Further, as for the points of connection of the inductiveelement and the damper resistor according to the invention areconcerned, so long as they are connected in parallel with the primarywinding of the transformer in an equivalent manner, sufficient effectscan be obtained. Moreover, the driving element according to theinvention is not limited to the complementary circuit, but it ispossible to employ a push-pull circuit or an SEPP (Single EndedPush-Pull) circuit.

INDUSTRIAL APPLICABILITY

As described above, the drive circuit for a switching power supply,according to the invention, includes the inductive element having aninductance value smaller than at least a value of an excitationinductance of the primary winding and allowing series resonance to occurbetween the capacitive element and the inductive element itself, so thatthe resonance frequency of the resonance phenomenon caused by thecapacitive element and the inductive element upon stoppage of operationfor generating power is increased. As a result, it is possible to reducethe ON time period of the main switching element, whereby the drivecircuit for a switching power supply can be realized which is capable ofpreventing breakage of the main switching element and the switchingtransformer connected thereto. Further, since it is possible to increasethe duty ratio of the drive signal, the drive circuit is realized whichpermits an increase in the range of switching control.

What is claimed is:
 1. A drive circuit for a switching power supply,comprising the drive circuit and a main switching element, the drivecircuit comprising: a driving element that generates a drive signal fordriving said main switching element; a capacitive element; a transformerhaving a primary winding and a secondary winding, said primary windingbeing connected to said driving element via said capacitive element,said primary winding receiving said drive signal, said secondary windingdelivering said drive signal to said main switching element; and aninductive element connected in series with said capacitive element, saidinductive element having an inductance value smaller than a value of anexcitation inductance of said primary winding and allowing seriesresonance to be produced between said capacitive element and saidinductive element.
 2. The drive circuit according to claim 1, whereinsaid capacitive element and said inductive element have respectiveelement constants that cause said series resonance to have a resonancefrequency exceeding one fifth of a frequency of said drive signal. 3.The drive circuit according to claim 1, wherein said capacitive elementand said inductive element have said respective element constants thatcause said series resonance to have a resonance frequency exceeding afrequency of said drive signal.
 4. The drive circuit according to claim1, wherein said inductive element is connected in parallel with saidprimary winding.
 5. The drive circuit according to claim 1, wherein aseries circuit is connected in parallel with said primary winding, saidseries circuit being formed by said inductive element and a damperresistor.
 6. The drive circuit according to claim 2, wherein saidinductive element is connected in parallel with said primary winding. 7.The drive circuit according to claim 2, wherein a series circuit isconnected in parallel with said primary winding, said series circuitbeing formed by said inductive element and a damper resistor.
 8. Thedrive circuit according to claim 3, wherein said inductive element isconnected in parallel with said primary winding.
 9. The drive circuitaccording to claim 3, wherein a series circuit is connected in parallelwith said primary winding, said series circuit being formed by saidinductive element and a damper resistor.
 10. The drive circuit accordingto claim 1, wherein said switching power supply further comprises acontrol circuit that generates a switching signal dependent on afeedback signal based on an output from said main switching element, andapplies said switching signal to said driving element; said drivingelement generating said drive signal in synchronism with said switchingsignal; and said capacitive element comprising a capacitor having acapacitance value as an element constant, and said capacitance valuesatisfying the following relationship: 20·Ciss≦C≦100·Ciss wherein Crepresents said capacitance value, and Ciss represents an inputcapacitance of said main switching element; and said inductive elementcomprising an inductor having said inductance value as an elementconstant, and said inductance value satisfying the followingrelationship: 2·π·(L·C)^(0.5)≦5/fSW wherein L represents said inductancevalue, and fSW represents a frequency of said driving element.
 11. Thedrive circuit according to claim 1, wherein said switching power supplyfurther comprises a control circuit that generates a switching signaldependent on a feedback signal based on an output from said mainswitching element, and applies said switching signal to said drivingelement; said driving element generating said drive signal insynchronism with said switching signal; and said capacitive elementcomprising a capacitor having a capacitance value as an elementconstant, and said capacitance value satisfying the followingrelationship: 20·Ciss≦C≦100·Ciss wherein C represents said capacitancevalue, and Ciss represents an input capacitance of said main switchingelement; and said inductive element comprising an inductor having saidinductance value as an element constant, and said inductance valuesatisfying the following relationship: 2·π·(L·C)^(0.5)≦5/fSW wherein Lrepresents said inductance value, and fSW represents a frequency of saiddriving element.
 12. The drive circuit according to claim 1, whereinsaid driving element comprises a complementary circuit formed of a npntransistor and a pnp transistor, and wherein said main switching elementcomprises an n-channel MOS FET.